1. Field of the Invention
The present invention relates to a method of manufacturing a plurality of chips of integrated circuits on a circuit substrate, and more particularly to a method of manufacturing chips which includes a process of inspecting integrated circuits on a circuit substrate.
2. Description of the Related Art
It has been the general practice to mass-produce chips of integrated circuits by arranging a number of integrated circuits on a surface of a silicon wafer as a circuit substrate and cutting the silicon wafer into a number of chips carrying the respective integrated circuits. In the mass-production of integrated circuits, the integrated circuits are inspected by various inspection processes in a plurality of stages. One of the inspection processes is a burn-in test for checking characteristic changes of integrated circuits while applying stresses to the integrated circuits.
There are various different processes for conducting the burn-in test. According to one of the processes, integrated circuits on a silicon wafer are inspected before the silicon wafer is severed into chips. Specifically, a test probe is connected to an electrode pad of each of the integrated circuits, and supplies a power supply voltage and a test signal to the electrode pad to check characteristics of each of the integrated circuits.
The above characteristic inspection is carried out successively on the integrated circuits on the silicon wafer. When the characteristic inspection is completed, probe electrodes for applying stresses are connected to the respective electrode pads of all the integrated circuits on the silicon wafer, and supply a power supply voltage higher than a rated level to the electrode pads thereby apply stresses to the integrated circuits.
After the stresses have been applied to all the integrated circuits for a preset period of time, the probe electrodes for applying stresses are removed from the respective integrated circuits. Then, the test probe is connected to inspect the characteristics of the integrated circuits successively. In this manner, the characteristics of the integrated circuits before and after they are stressed are determined. Those integrated circuits whose characteristics have exhibited profound changes after they have been stressed and those integrated circuits whose characteristics are poor after they have been stressed are judged as being defective.
After the burn-in test has been completed, the silicon wafer is severed into chips carrying the respective integrated circuits, and any chips carrying integrated circuits which have been judged as being defective are rejected, producing chips carrying accepted integrated circuits.
However, the conventional burn-in test has suffered the following problems:
In order to apply uniform stresses to all the integrated circuits on the silicon wafer in the burn-in test, it is necessary to connect the probe electrodes for applying stresses to the respective electrode pads of all the integrated circuits on the silicon wafer.
Therefore, there is a need for a probe card having a great number of probe electrodes to be connected to the respective electrode pads of all integrated circuits on silicon wafers. Since it is not easy to produce such a probe card, the productivity of chips is lowered. Furthermore, it is difficult to bring the many probe electrodes on the probe card into accurate contact with the respective electrode pads on the silicon wafer.
Inasmuch as the characteristics of the integrated circuits are inspected before and after they are stressed in the burn-in test, some integrated circuits may be judged as being defective in the first inspection session. However, the results of the first inspection session are not effectively utilized because the probe card has its probe electrodes connected uniformly to all the integrated circuits including any integrated circuits which may have been judged as being defective in the first inspection session.
The above problems can be solved by connecting a probe electrode successively to all the integrated circuits for stressing them as with the characteristic inspection stages and applying stresses to the integrated circuits with the probe electrode. This process is, however, extremely time-consuming as stresses need to be applied to each of the integrated circuits for a preset period of time.